Modern SoC designs can include 10s of millions of DFFs,Reset signals use valuable routing resources, making physical design more challenging,The current trend is to reset only a subset of registers,but manually selecting registers to reset can be challenging.

 Modern SoC designs use multiple power domains,Retention registers are added to ensure data integrity during sleep/low power mode.States are stored in retention registers during power down and States are restored when the block is powered up.Retention registers. Retention register selection is also painful work.

 RegOPT optimizes registers to reset / retain 2 ways:

Static formal analysis selects registers to not reset / retain assuming all possible initial states or reset of retention

Dynamic formal analysis analyzes real reset and restore sequences to further improve the results by applying software/firmware reset / power-up emulation

 

 

 

 

 

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